A. Field of the Invention
The present invention relates to a semiconductor device such as a high breakdown voltage IC (integrated circuit) in which high breakdown voltage lateral semiconductor elements and low breakdown voltage semiconductor elements for controlling are integrated together on the same substrate by applying a dielectric isolation technique thereto. In particular, the invention relates to a semiconductor device forming a one-chip inverter in which lateral IGBTs (insulated gate bipolar transistors) and lateral FWDs (free wheeling diodes) are mounted on the same substrate together with driving circuits of the respective IGBTs, a control circuit and a level shift circuit.
B. Description of the Related Art
In recent years, in high breakdown voltage semiconductor devices, a high breakdown voltage power IC has been developed in which power switching elements such as IGBTs and circuits for driving, controlling and protecting the IGBTs are integrated together on one semiconductor substrate. An element isolation technique such as that of junction isolation or dielectric isolation is used to mutually isolate the elements in such a high breakdown voltage power IC.
In a structure using dielectric isolation, capacitance per unit area in an isolated region is much smaller than that for a structure in which junction isolation is used. Thus, the structure has an advantage of hardly causing damage or malfunction of the semiconductor device due to latch-up induced by a parasitic element. In addition, a dielectric isolation structure can eliminate generation of a leak current caused by light irradiation under an environment of a strong radiation, which occurs in an element with a junction isolation structure.
Because of the above advantage of a dielectric isolation structure, a one-chip inverter is developed by using a dielectric isolation technique. In the one-chip inverter, lateral IGBTs and lateral FWDs are mounted together on the same substrate with a control element for controlling the IGBTs and the FWDs. The advantage of the one-chip inverter over a conventional structure in which power element chips and control element chips are separately provided is that an inverter device can be miniaturized with a considerable reduction in chip surface mounting areas and is highly reliable because of the reduction in the number of electrical connections between chips with bonding wires.
In FIG. 9, an arrangement of a general inverter circuit is shown. As shown in FIG. 9, a power device used for driving an electrical machine (not shown) such as a three-phase motor is made up of six IGBTs (Q1, Q2, Q3, Q4, Q5 and Q6) and six FWDs (D1, D2, D3, D4, D D6) connected in parallel to the respective IGBTs, with which a bridge circuit is formed. Anodes of the FWDs D1, D2, D3, D4, D5 and D6 are connected to emitters of the IGBTs of Q1, Q2, Q3, Q4, Q5 and Q6, respectively. Cathodes of the FWDs are connected to collectors of the respective IGBTs.
A direct-current voltage is applied between collectors of the IGBTs Q1, Q2 and Q3, upper arm switching elements in the U-phase, the V-phase and the W-phase, respectively, and emitters of the IGBTs Q4, Q5 and Q6, lower arm switching elements in the U-phase, the V-phase and the W-phase, respectively. The direct-current voltage is obtained by an AC power source 1, a converter 2 and a capacitor C.
Gates of the IGBTs Q1, Q2 and Q3 on the upper arm side are connected to corresponding output stage elements 3a, 3b and 3c, respectively. Gates of the IGBTs Q4, Q5 and Q6 on the lower arm side are connected to respective corresponding output stage elements (not shown) provided in control circuit 4. In other word, the IGBTs Q1, Q2, Q3, Q4, Q5 and Q6 are turned on and off on the basis of output signals from the respective corresponding output stage elements. In FIG. 9, in order to avoid making the figure complicated, illustration of connection between each gate and a corresponding output stage element is omitted.
A control signal for determining which ones of the IGBTs Q1, Q2, Q3, Q4, Q5 and Q6 are turned on and which ones are turned off is transmitted from control circuit 4 on the basis of a signal supplied from a microcomputer (not shown). Control signals for the IGBTs Q1, Q2 and Q3 on the upper arm side are subjected to voltage adjustment by level shift circuit 5 before being supplied to output stage elements 3a, 3b and 3c through driving circuits 6a, 6b and 6c corresponding thereto, respectively. Control signals for the IGBTs Q4, Q5 and Q6 on the lower arm side are supplied to their illustration-omitted respective output stage elements through their respective corresponding driving circuits (not shown) provided in control circuit 4.
FIG. 10 is a plan view schematically showing an arrangement of a principal part for the upper arm of the U-phase in a related one-chip inverter. As shown in FIG. 10, in the related one-chip inverter (a part of the upper arm for the U-phase) 10, on a SOI (silicon on insulator) substrate, there are formed control circuit 11 that outputs a control signal to a driving circuit for each of the U-phase, the V-phase and the W-phase on the basis of an input signal, high breakdown voltage NMOSFETs (N-channel insulated gate field effect transistors each using an oxide film as a gate insulator film) 12a and 12b each forming a level shift element in a level shift circuit, lateral IGBT 13 as a switching element on the U-phase upper arm, lateral FWD 14 connected in parallel to lateral IGBT 13, output stage element 15 supplying a switching signal to lateral IGBT 13, and driving circuit 16 producing an output signal to output stage element 15 on the basis of signals supplied from drain electrodes 17a and 17b of the high breakdown voltage NMOSFETs 12a and 12b (level shift elements) through wires 18a and 18b, respectively.
A region for forming each of the circuits and the elements is separated from others by trench isolation region 19. FIG. 10, however, only shows circuits relating to the key functions of the inverter without showing protection circuits included in the driving circuit and the control circuit, and circuits having other functions (the same is true for any other figures). Moreover, in some cases, for the level shift element, instead of the high breakdown voltage NMOSFET for a level-up circuit, a high breakdown voltage PMOSFET (P-channel MOSFET) for a level-down circuit is mounted.
FIG. 11 is a vertical cross sectional view taken on line G–G′ in FIG. 10 showing a cross sectional structure of high breakdown voltage NMOSFET 12a (level shift element). As shown in FIG. 11, SOI substrate 20 has a structure in which first semiconductor substrate 21 as a supporting substrate, and second semiconductor substrate 23 as a semiconductor layer in which element structures are formed, are layered with oxide film 22 as an insulator layer in between. Drain electrode 17a of the high breakdown voltage NMOSFET 12a is provided at the center of the high breakdown voltage NMOSFET 12a. High breakdown voltage junction terminating structure 24 is formed around drain electrode 17a, and is made up of a RESURF (reduced surface field) structure such as a double RESURF or a single RESURF.
Gate electrode 25 and source electrodes 26a and 26b of the high breakdown voltage NMOSFET 12a are formed in a part of the peripheral section of high breakdown voltage junction terminating structure 24. P-diffused layers 27a and 27b are provided on the surface of high breakdown voltage junction terminating structure 24 to achieve a high breakdown voltage by a RESURF effect. Trench isolation region 19 is provided around high breakdown voltage NMOSFET 12a. Oxide film 28 is formed on each side wall of trench isolation region 19. An inside part between oxide films 28 is filled with polycrystalline silicon 29.
As shown in FIG. 11, in a related one-chip inverter, wire 18a connected to drain electrode 17a of high breakdown voltage NMOSFET 12a traverses over high breakdown voltage junction terminating structure 24. This causes an area between wire 18a and second semiconductor substrate 23 to which a high voltage of the order of 600V, for example, is applied. Therefore, interlayer insulator film 30 such as an oxide film provided between high voltage wire 18a and second semiconductor substrate 23 must be thick enough. Thin interlayer insulator film 30 causes an electric potential of high voltage wire 18a to affect an electric potential distribution in the substrate, which results in degradation in a breakdown voltage of high breakdown voltage NMOSFET 12a. Furthermore, possible breakdown of interlayer insulator film 30 is caused at a sudden increase in the electric potential of drain electrode 17a. 
The same is true for an interlayer insulator film provided between wire 18b, connected to drain electrode 17b of the other high breakdown voltage NMOSFET 12b shown in FIG. 10, and second semiconductor substrate 23. Moreover, the same is also true about a part for the upper arm of the V-phase and a part for the upper arm of the W-phase that have the same arrangement as that of the above-described part for the upper arm of the U-phase.
The inventors previously reported that use of a self-shielding technique eliminates the structure, in which a wire at a high electric potential traverses over a substrate at the ground (GND) level with an insulator in between, to thereby make it possible to actualize an IC with a high breakdown voltage of 1000V or more (see Fujihira et al., “Self-shielding: New High-Voltage Inter-Connection Technique for HVICs,” Proc. 8th Int. Symp. Power Semiconductor Devices and ICs, Maui, 1996, IEEE (1996), pp 231–234). Various proposals are presented about the self-shielding technique (see, for example, Japanese Patent No.3,214,818, JP-A-9-55498 and U.S. Pat. No. 6,124,628).
FIG. 12 is a plan view schematically showing an arrangement of a principal part for an upper arm of the U-phase in a related inverter device in which the self-shielding technique is applied to a multi-chip arrangement. As shown in FIG. 12, control circuit 11, output stage element 15 and driving circuit 16 are formed into high breakdown voltage IC chip 31. IGBT 32 and FWD 33 are formed into their respective chips different from high breakdown voltage IC chip 31.
Output stage element 15 and driving circuit 16 are formed in a region surrounded by high breakdown voltage junction terminating structure 34 made up of a loop-like RESURF structure in high breakdown voltage IC chip 31. Output stage element 15 is electrically connected to gate electrode 35 and emitter electrode 36 of IGBT 32 through bonding wires 37 and 38, respectively.
FIG. 13 is a vertical cross sectional view taken on line H–H′ in FIG. 12, which view shows a cross sectional structure of high breakdown voltage NMOSFET 12a as a level shift element. As shown in FIG. 13, drain electrode 17a of high breakdown voltage NMOSFET 12a is formed at one end of high breakdown voltage junction terminating structure 34. At the other end of high breakdown voltage junction terminating structure 34, gate electrode 25 and source electrodes 26a and 26b of high breakdown voltage NMOSFET 12a are formed. A cross sectional structure of the other high breakdown voltage NMOSFET 12b is the same as that shown in FIG. 13. A structure of a part for the upper arm of the V-phase and a structure of a part for the upper arm of the W-phase are the same as the structure of the part for the upper arm of the U-phase.
As explained above, in the related one-chip inverter, thick interlayer insulator film 30 is necessary between high voltage wire 18a and second semiconductor substrate 23. However, there is a limit to the thickness of the insulator film such as an oxide film that can be formed on the substrate in respect to manufacturing cost. The thickness of an interlayer insulator film put to practical use under the present situation is of the order of 6 μm in a one-chip inverter with a 600V breakdown voltage. Compared with this, realization of a one-chip inverter of 1200V breakdown voltage class with the same structure as that of one with the 600V breakdown voltage necessitates that the interlayer insulator film under the high voltage wire be formed with a thickness exceeding 10 μm for ensuring high reliability. This makes it difficult to produce the chips at low cost.
The present invention was made in view of the above problem with an object of providing a high breakdown voltage semiconductor device at low cost in which device power elements and a driving circuit for driving the elements are integrated together in the same chip. A semiconductor device in which logic elements for controlling the power elements are also integrated together in the above chip. The present invention is directed to overcoming, or at least reducing, the effects of one or more of the problems set forth above.